EDN

Phase-Locked Loop Applications

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...
EDN

Free phase-locked loop (PLL) analysis software

Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...
Hackaday

Learn Something About Phase Locked Loops

But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing its output by 100 will give you a signal you can lock to a 1 MHz crystal oscillator which is, of course, trivial to build.
AZOM

Principles of Phase-Locked Loops (PLL)

Learn about the working principles of Phase-Locked Loops (PLL) and why they are widely used for applications where frequency tracking, resonance driving, and oscillator control are required.
Electronic Design

Measure Phase-Locked Loops With A Spectrum Analyzer

A general-purpose vector signal analyzer offers a low-cost, flexible option for measuring the frequency settling time of PLLs. By Douglas Olney, Keithley Instruments Inc. The frequency-settling time ...
Nature

Radiation-Hardened Phase-Locked Loop Circuits

Radiation-hardened phase-locked loop (PLL) circuits represent a critical advancement in safeguarding electronic systems against the deleterious effects of ionising radiation. These circuits are ...
Hackaday

phase lock loop

The phase locked loop, or PLL, is a real workhorse of circuit design. It is a classic feedback loop where the phase of an oscillator is locked to the phase of a ...
EurekAlert!

Combating fractional spurs in phase locked loops to improve wireless system performance in Beyond 5G

Two innovative design techniques lead to substantial improvements in performance in fractional-N phase locked loops (PLLs), report scientists from Tokyo Tech. The proposed methods are aimed to ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 1)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
EurekAlert!

Figure 2. Die micrograph of the proposed digital phase locked loop (PLL) (IMAGE)

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...
Business Wire

Analog Devices’ 4-GHz PLL Synthesizer Offers Leading Phase Noise Performance

AMSTERDAM--(BUSINESS WIRE)--Analog Devices, Inc. (ADI), a global leader in high-performance semiconductors for signal-processing applications and leading provider of RF ICs (radio frequency integrated ...