insideHPC

Astera Labs Says Its CXL Memory Controller Boosts Server Memory Bandwidth by 50%

SANTA CLARA, CA, U.S. – September 19, 2023 – Astera Labs today said its Leo Memory Connectivity Platform is the industry’s first Compute Express Link (CXL) memory controller that increases server ...
Business Wire

ASE Drives Latency and Bandwidth Innovation with VIPack™ Fanout Package-on-Package

SUNNYVALE, Calif.--(BUSINESS WIRE)--Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced its most advanced ...
TweakTown

China's Innosilicon LPDDR6/5X memory controller IP delivered to first customers, up to 14.4Gbps

Chinese chip maker Innosilicon has announced its new LPDDR6/5X memory controller IP provided to its first customers in China, ...
Semiconductor Engineering

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 3

This is the third and final of a series from Alphawave Semi on HBM4 and gives and examines custom HBM implementations. Click here for part 1, which gives an overview of the HBM standard, and here for ...
EDN

Memory controllers offer higher memory bandwidth

Microchip Technology Inc. has expanded its serial-attached memory controller portfolio with the new SMC 2000 series of Compute Express Link (CXL) based smart memory controllers for data-center ...
ZDNet

Storage surprise: Why latency is more important than bandwidth

Bandwidth is a simple number that people think they understand. The bigger the number, the faster the storage. We'll see more change in the next decade than we've ever seen before in computer data ...
Business Wire

Kioxia Achieves Successful Prototyping of 5TB Large-Capacity and 64GB/s High-Bandwidth Flash Memory Module

TOKYO--(BUSINESS WIRE)--Kioxia Corporation, a world leader in memory solutions, has successfully developed a prototype of a large-capacity, high-bandwidth flash memory module essential for large-scale ...
ZDNet

Three ways to fix DRAM's latency problem

In a brilliant PhD thesis, Understanding and Improving the Latency of DRAM-Based Memory Systems, Kevin K. Chang of CMU tackles the DRAM issue, and suggests some novel architectural enhancements to ...
Business Insider

Microchip Enters Memory Infrastructure Market with Serial Memory Controller for High-performance Data Center Computing

CHANDLER, Ariz., Aug. 5, 2019 /PRNewswire/ -- As the computational demands of artificial intelligence (AI) and machine learning workloads accelerate, traditional parallel attached DRAM memory has ...
EDN

Fast controller IP harnesses HBM3 memory

Comprising fully integrated PHY and digital controller IP, the Rambus HBM3-ready memory interface subsystem operates at up to 8.4 Gbps. This data rate is more than double that of the Rambus HBM2E ...
Semiconductor Engineering

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 1

This is the first of a three-part series on HBM4 and gives an overview of the HBM standard. Part 2 will provide insights on HBM implementation challenges, and part 3 will introduce the concept of a ...