SAN JOSE, Calif. — ASIC and FPGA verification tool vendor Aldec Inc. has added a cosimulation wizard to its Active-HDL simulation environment to connect the environment to Mathworks' Simulink. The new ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...

As total system complexity grows, so does verification complexity. To speed simulation time and improve functional coverage of the RTL ASIC under test, the transactors used for RTL verification must ...

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...

Doubling the performance of the previous release, Version 6.2 of Active-HDL is an integrated, Windows-based HDL design and simulation environment. Behavioral, gate-level, and timing simulation ...

HENDERSON, Nev. & MOUNTAIN VIEW, Calif.--March 12, 2007--Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of ...

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And ...