EDN

Functional coverage metrics — the next frontier

“The ideal is to achieve comprehensive validation without redundant effort. Coverage metrics helps approximate this ideal by acting as heuristic measures that quantify verification completeness, and ...
Semiconductor Engineering

Recipe To Catch Bugs Faster Using Machine Learning

We all agree that verification and debug take up a significant amount of time and are arguably the most challenging parts of chip development. Simulator performance has consistently topped the charts ...
New Electronics

Cadence and Imperas support NSITEXE in development of automotive RISC V Vector processor IP

Imperas Software and Cadence Design Systems have collaborated to enable NSITEXE, part of the DENSO Corporation, to develop a RISC-V-based processor IP for functional safety and next-generation ...
Design-Reuse

Functional Coverage Analysis for IP Cores and an Approach to Scaledown Overall Simulation Time

This paper presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real ...
Design-Reuse

Combined coverage methodology speeds verification

Engineers are creating designs larger than ever before. As gate counts exceed one million, verification methodologies have failed to adjust, turning functional verification into the main bottleneck in ...
Business Wire

Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation With up to 5X Faster Regressions

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence ® Xcelium ™ Logic Simulator has been enhanced with machine learning technology (ML), called ...